1. Field of the Invention
The present invention relates to a level conversion circuit, and more particularly to a level conversion circuit for converting a CMOS (Complementary Metal Oxide Semiconductor) level signal to an ECL (Emitter-Coupled Logic) level signal.
2. Description of the Prior Art
Recently, so-called Bi-CMOS circuits have become popular in semiconductor circuit fields. The Bi-CMOS circuits have a combined structure of bipolar device circuits and CMOS device circuits commonly formed on one single chip Bipolar circuits such as ECL LSIs (Large Scale Integrated circuits) typically provide fast circuit speeds, reduced delay per unit load, and have historical been the predominate technology applied in ICs (Integrated Circuits). CMOS circuits provide high noise immunity, high input impedance, and low power consumptions, and have rapidly gained acceptance in the industry. Thus Bi-CMOS circuits may have the features of both the bipolar circuits and the CMOS circuits.
To use ECL device circuits together with CMOS device circuits, the input-output levels of both circuits must be matched and in particular, an interface circuit for converting a CMOS logic level (high level; power source potential, for example, 5.0 volts, low level; ground potential, i.e., 0 volts) to an ECL logic level (high level; for example, --0.7 volts, low level; for example, --2.5 volts) is necessary.
One previously known circuit converting the CMOS logic level to the ECL logic level comprises a pair of push-pull bipolar transistors, e.g., NPN transistors. The upper NPN transistor has a collector terminal connected to a first potential source and a source terminal of a MOS device, e.g., P-channel MOS transistor (referred as PMOS transistor hereafter), an emitter terminal connected to an output terminal and the collector terminal of the lower bipolar transistor, and a base terminal connected to an input terminal and the gate terminals of the PMOS transistor and an N-channel MOS transistor (referred as NMOS transistor hereafter) which is connected to the PMOS transistor so that they constitute a CMOS structure. The emitter terminal of the lower NPN transistor is connected to a second potential source and the source terminal of the NMOS transistor, and a base terminal connected to the drain terminals of the PMOS transistor and the NMOS transistor. However, this circuit has a low impedance at the input terminal since the input terminal is connected to the base terminal of the upper NPN transistor, and as the output of the circuit switches from low to high, the lower NPN transistor is slow to turn off causing a slow transition to the high output.
Thus, what is needed is an IC combining CMOS and bipolar technology having a high input impedance, improved switching characteristics, low power consumption, and high noise immunity.